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6-Bit, Programmable 2-/3-/4-Phase, Synchronous Buck Controller ADP3191
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase 14.5 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers PWM Flex-ModeTM architecture for excellent load transient performance Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes 6-bit digitally programmable 0.8375 V to 1.6 V output Programmable short circuit protection with programmable latch-off delay
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ
14
RT
13
SHUNT REGULATOR (ADP3191 ONLY) OSCILLATOR EN 11 GND 19 DAC+150mV CSREF CURRENT BALANCING CIRCUIT CMP RESET 2-/3-/4-PHASE DRIVER LOGIC CMP DAC-250mV CMP PWRGD 10 DELAY RESET CURRENT LIMIT
24 26
UVLO SHUTDOWN AND BIAS
SET CMP RESET
EN
27
PWM1
PWM2
RESET
25
PWM3
PWM4
CROWBAR
23 22
SW1 SW2 SW3 SW4 CSSUM CSREF
APPLICATIONS
Desktop PC power supplies for Next-generation Intel(R) processors VRM modules Games consoles
ILIMIT 15 EN CURRENT LIMIT CIRCUIT
21 20
17
DELAY 12
16
18
CSCOMP
GENERAL DESCRIPTION
The ADP3191/ADP3191A1 are highly efficient, multiphase, synchronous buck switching regulator controllers optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high performance Intel processors. They use an internal 6-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6 V. The devices use a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3191/ADP3191A also include programmable, no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is always optimally positioned for a system transient. The ADP3191/ADP3191A also provide accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU.
COMP
9
SOFT START
8
FB
PRECISION REFERENCE
VID DAC
ADP3191/ ADP3191A
4 5 6
7
1
2
3
FBRTN
VID4
VID3
VID2
VID1
VID0
VID5
Figure 1.
The ADP3191 is a replacement for the ADP3181. A built-in shunt regulator allows the part to be connected to the 12 V system supply through a series resistor. The devices are specified over the commercial temperature range of 0C to 85C and are available in a 28-lead TSSOP and a 28-lead QSOP.
1
Protected by U. S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05648-001
ADP3191 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics and Test Circuits............... 7 Theory of Operation ........................................................................ 8 Startup Sequence .......................................................................... 8 Master Clock Frequency.............................................................. 8 Output Voltage Differential Sensing .......................................... 8 Output Current Sensing .............................................................. 8 Active Impedance Control Mode............................................... 9 Current-Control Mode and Thermal Balance.......................... 9 Voltage Control Mode.................................................................. 9 Soft Start ........................................................................................ 9 Current-Limit, Short-Circuit, and Latch-Off Protection...... 10 Dynamic VID.............................................................................. 10 Power Good Monitoring ........................................................... 12 Output Crowbar ......................................................................... 12 Output Enable and UVLO ........................................................ 12 Application Information................................................................ 14 Setting the Clock Frequency ..................................................... 14 Soft Start and Current-Limit Latch-Off Delay Times ........... 14 Inductor Selection ...................................................................... 14 Designing an Inductor............................................................... 15 Output Droop Resistance.......................................................... 15 Inductor DCR Temperature Correction ................................. 16 Output Offset .............................................................................. 16 COUT Selection ............................................................................. 17 Power MOSFETs......................................................................... 18 Ramp Resistor Selection............................................................ 19 COMP Pin Ramp ....................................................................... 19 Current-Limit Setpoint.............................................................. 19 Feedback Loop Compensation Design.................................... 19 CIN Selection and Input Current di/dt Reduction.................. 21 Tuning the ADP3191/ADP3191A............................................ 22 Replacing the ADP3181 with the ADP3191........................... 24 Choosing Between the ADP3191 and the ADP3191A ........ 24 RAMPADJ Filter......................................................................... 24 Shunt Resistor Design................................................................ 25 Layout and Component Placement.............................................. 26 General Recommendations....................................................... 26 Power Circuitry Recommendations ........................................ 26 Signal Circuitry Recommendations......................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
3/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADP3191 SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0C to +85C, unless otherwise noted.1 Table 1.
Parameter ERROR AMPLIFIER Output Voltage Range Accuracy Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current, Input Voltage Low Input Current, Input Voltage High Pull-Up Resistance Internal Pull-Up Voltage VID Transition Delay Time 2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Symbol VCOMP VFB VFB IFB IFBRTN IO(ERR) GBW(ERR) Conditions Min 0 -14.5 0.05 15.5 100 500 20 25 Typ Max VCC +14.5 Unit V mV % A A A MHz V/s V V A A k V ns ns MHz kHz kHz kHz V mV A mV nA MHz V/s V mV V A mV k A %
Relative to nominal DAC output, referenced to FBRTN, CSSUM = CSCOMP VCC = 4.75 V to 5.25 V
14 FB forced to VOUT - 3% COMP = FB CCOMP = 10 pF
17 140
VIL(VID) VIH(VID) IIL(VID) IIH(VID) RVID
0.4 0.8 VID(X) = 0 V VID(X) = 1.25 V 35 1.0 400 400 0.25 155 -25 5 60 1.2 -35 15 85
VID code change to FB change VID code change to 11111 to PWM going low fOSC fPHASE
Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current CURRENT BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching3 CURRENT LIMIT COMPARATOR Output Voltage Normal Mode In Shutdown Output Current, Normal Mode Maximum Output Current2
VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA)
TA = +25C, RT = 225 k, 4-phase TA = +25C, RT = 100 k, 4-phase TA = +25C, RT = 30 k, 4-phase RT = 100 k to GND RAMPADJ - FB
1.8 -50 0 -3 -50
200 400 600 2.0
2 245
2.3 +50 100 +3 +50
CSSUM - CSREF
VFB ICSCOMP VSW(X)CM RSW(X) ISW(X) ISW(X)
CCSCOMP = 10 pF CSSUM and CSREF See Figure 5
10 10 0 -77 0.05 -80 500 -600 12 5 -5 +200 28 17 +5 3 -83 VCC
SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V
20 11
VILIMIT(NM) VILIMIT(SD) IILIMIT(NM)
EN > 0.8 V, RILIMIT = 250 k EN < 0.4 V, IILIMIT = -100 A EN > 0.8 V, RILIMIT = 250 k
2.8
3 12
3.3 400
60
V mV A A
Rev. 0 | Page 3 of 28
ADP3191
Parameter Current Limit Threshold Voltage Current Limit Setting Ratio DELAY Normal Mode Voltage DELAY Overcurrent Threshold Latch-Off Delay Time SOFT START Output Current, Soft Start Mode Soft Start Delay Time ENABLE INPUT Input Low Voltage Input High Voltage Input Current POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Power Good Delay Time During Soft Start VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY--ADP3191 VCC DC Supply Current UVLO Threshold Voltage UVLO Hysteresis SUPPLY--ADP3191A VCC DC Supply Current UVLO Threshold Voltage UVLO Hysteresis
1 2
Symbol VCL VDELAY(NM) VDELAY(OC) tDELAY IDELAY(SS) tDELAY(SS)
Conditions VCSREF - VCSCOMP, RILIMIT = 250 k VCL/IILIMIT RDELAY = 250 k RDELAY = 250 k RDELAY = 250 k, CDELAY = 12 nF During startup, DELAY < 2.8 V RDELAY = 250 k, CDELAY = 12 nF, VID code = 011111
Min 105 2.8 1.6
Typ 125 10.4 3 1.9 1.5 20 1
Max 145 3.3 2.2
Unit mV mV/A V V ms A ms
15
25
VIL(EN) VIH(EN) IIL(EN) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = 4 mA RDELAY = 250 k, CDELAY = 12 nF, VID code = 011111
0.4 0.8 -1 -180 230 -250 300 225 +1 -300 370 400
V V A mV mV mV ms
1 100 250 200 300 730 250 400 160 5 5 20 7 0.9 5 7 4.0 0.9 500
VCROWBAR tCROWBAR
Relative to nominal DAC output Relative to FBRTN Overvoltage to PWM going low Blanking time
270 620 100
350 840
s ns mV mV s ns mV V V mA V V V mA V V
VOL(PWM) VOH(PWM) VCC VUVLO
IPWM(SINK) = -400 A IPWM(SOURCE) = +400 A VSYSTEM = 12 V, RSHUNT = 300 , see Figure 4
4.0 4.75
VCC rising VSYSTEM = 5 V, RSHUNT = 10 , see Figure 4
6.3
30 8.0
VCC VUVLO VCC rising
4.75 3.7
12 4.3
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design, not production tested. 3 Relative current matching from each phase to the average of all four phases.
Rev. 0 | Page 4 of 28
ADP3191 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC VID Pins FBRTN SW1 to SW4 All Other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to +0.3 V -5 V to +25 V -0.3 V to VCC + 0.3 V -65C to +150C 0C to +85C 125C 100C/W 300C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 28
ADP3191 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID4 1 VID3 2 VID2 3 VID1 4 VID0 5 VID5 6 FBRTN 7 FB 8 COMP 9 PWRGD 10 EN 11 DELAY 12 RT 13 RAMPADJ 14
28 27 26 25 24
VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT
05648-002
ADP3191/ ADP3191A
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 to 6 Mnemonic VID4 to VID0, VID5 Description Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to 1.6 V (see Table 2). Leaving all the VID pins open results in ADP3191/ADP3191A going into a "No CPU" mode, shutting off their PWM outputs and pulling the PWRGD output low. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no-load offset point. Error Amplifier Output and Compensation Point. Power Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Soft Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3191/ADP3191A EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3110A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the ADP3191/ADP3191A to operate as a 2-, 3-, or 4-phase controller. ADP3191: A 240 resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V. ADP3191A: A 10 resistor should be placed between the 5 V system supply and the VCC pin to ensure 5 V.
7 8 9 10 11 12 13 14 15
FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ ILIMIT
16
CSREF
17 18 19 20 to 23 24 to 27
CSSUM CSCOMP GND SW4 to SW1 PWM4 to PMW1 VCC
28
Rev. 0 | Page 6 of 28
ADP3191 TYPICAL PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
05648-027
12V 300
28
MASTER CLOCK FREQUENCY (MHz)
ADP3191
VCC
CSCOMP
18
39k
100nF
17
CSSUM
1k
16
CSREF
1.0V
0 50 100 150 RT (k) 200 250 300
19
0
Figure 3. Master Clock Frequency vs. RT
Figure 5. Current Sense Amplifier VOS
ADP3191
12V
ADP3191A
5V
ADP3191 12V 240
ADP3191A 5V
ADP3191 ADP3191A
1 VID4 2 VID3 3 VID2
240
ADP3191/ADP3191A
VCC
28
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18
+
1F
100nF
200k
18
CSCOMP
6-BIT CODE
4 VID1 5 VID0 6 VID5 7 FBRTN 8 FB 9 COMP 10 PWRGD
200k
100nF CSSUM
17
V
16
CSREF
1.0V
19
GND
05648-023
1k
1.25V
11 EN 12 DELAY
VFB = FBV = 80mV - FBV = 0mV
20k 100nF
CSSUM 17 CSREF 16 ILIMIT 15 250k
05648-021
Figure 6. Positioning Voltage
12nF
250k
13 RT 14 RAMPADJ
Figure 4. Closed-Loop Output Voltage Accuracy
Rev. 0 | Page 7 of 28
05648-022
GND
VOS =
CSCOMP - 1V 40
ADP3191 THEORY OF OPERATION
The ADP3191/ADP3191A combine a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 6-bit VRD/VRM 10- and 10.1-compatible CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and MOSFETs. The multimode control of the ADP3191/ADP3191A ensures a stable, high performance topology for * * * * * * * * * Balancing currents and thermals between phases High speed response at the lowest possible switching frequency and output decoupling Minimizing thermal switching losses due to lower frequency operation Tight load line regulation and accuracy High current output for up to 4-phase operation Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component selection Flexibility in operation for tailoring design to low cost or high performance If the PWM output is grounded, it remains off. The PWM outputs are logic-level devices intended for driving external gate drivers, such as the ADP3110A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at the same time for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3191/ADP3191A is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3191/ADP3191A differential sense compares a high accuracy VID DAC and a precision reference to implement a low offset error amplifier. This maintains a worst-case specification of 9.5 mV differential sensing error over their full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
STARTUP SEQUENCE
During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3191/ADP3191A operate as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation, and grounding the PWM3 pin and the PWM4 pin programs 2-phase operation. When the ADP3191/ADP3191A are enabled, the controller outputs a voltage on PWM3 and PWM4 that is approximately 675 mV. An internal comparator checks each pin's voltage vs. a threshold of 300 mV. If the pin is grounded, it is below the threshold, and the phase is disabled. The output resistance of the PWM pins is approximately 5 k during this detection time. Any external pull-down resistance connected to the PWM pins should not be less than 25 k to ensure proper operation. PWM1 and PWM2 are disabled during the phase detection interval, which occurs during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 k resistance is removed, and it switches between 0 V and 5 V.
OUTPUT CURRENT SENSING
The ADP3191/ADP3191A provide a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. Sensing the load current at the output gives the total average current being delivered to the load. This is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system: * * * Output inductor DCR sensing without a thermistor for lowest cost Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements
Rev. 0 | Page 8 of 28
ADP3191
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF - CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning and as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors, so it can be made extremely accurate. External resistors can be placed in series with individual phases to create, if desired, an intentional current imbalance, such as when one phase has better cooling and can support higher currents. Resistor RSW1 through Resistor RSW4 (see the typical application circuit in Figure 9) can be used for adjusting thermal balance. It is best to have the ability to add these resistors during the initial design, so make sure that placeholders are provided in the layout. To increase the current in any given phase, make RSW for this phase larger (make RSW = 0 for the hottest phase, and do not change during balancing). Increasing RSW to only 500 makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE
A high gain bandwidth voltage mode error amplifier is used for the voltage-mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor (RB) and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RBB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage is negative with respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP.
B
ACTIVE IMPEDANCE CONTROL MODE
For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to equal the droop impedance of the regulator multiplied by the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response.
CURRENT-CONTROL MODE AND THERMAL BALANCE
The ADP3191/ADP3191A have individual inputs for each phase, which are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system, which has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning described previously. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Application Information section.
SOFT START
The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current-limit latch-off time. In UVLO, or when EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged with an internal 20 A current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of the VID DAC and CDLY, with a secondary effect from RDLY. Refer to the Application Information section for detailed information on setting CDLY. If EN is taken low or if VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft start cycle. Figure 7 shows a typical soft start sequence for the ADP3191/ADP3191A.
Rev. 0 | Page 9 of 28
ADP3191
This prevents the DELAY capacitor from discharging, so the 1.8 V threshold is never reached. The resistor has an impact on the soft start time because the current through it adds to the internal 20 A current source. During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. An inherent per phase current limit protects individual phases, if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage.
05648-008
Figure 7. Typical Start-Up Waveforms Channel 1: PWRGD, Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION
The ADP3191/ADP3191A compare a programmable currentlimit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current-limit threshold of 10.4 mV/A. If the difference in voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current-limit latch-off delay time is, therefore, set by the RC time constant discharging from 3 V to 1.8 V. The Application Information section discusses the selection of CDLY and RDLY. Because the controller continues to cycle the phases during the latch-off delay time, the controller returns to normal operation if the short is removed before the 1.8 V threshold is reached. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if a short circuit has caused the output voltage to drop below the PWRGD threshold, a soft start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3191/ADP3191A or by pulling the EN pin low for a short time. To disable the short-circuit latchoff function, the external resistor to ground should be left open, and a high value (>1 M) resistor should be connected from DELAY to VCC.
Figure 8. Overcurrent Latch-Off Waveforms Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3191/ADP3191A have the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the ADP3191/ADP3191A detect the change and ignore the DAC inputs for a minimum of 400 ns. This time prevents a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD and crowbar blanking functions for a minimum of 100 s to prevent a false PWRGD or crowbar event. Each VID change resets the internal timer.
Rev. 0 | Page 10 of 28
05648-009
ADP3191
Table 4. VID Codes for the ADP3191/ADP3191A
VID4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID2 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 VID1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 VID0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 VID5 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output No CPU No CPU 0.8375 V 0.8500 V 0.8625 V 0.8750 V 0.8875 V 0.9000 V 0.9125 V 0.9250 V 0.9375 V 0.9500 V 0.9625 V 0.9750 V 0.9875 V 1.0000 V 1.0125 V 1.0250 V 1.0375 V 1.0500 V 1.0625 V 1.0750 V 1.0875 V 1.1000 V 1.1125 V 1.1250 V 1.1375 V 1.1500 V 1.1625 V 1.1750 V 1.1875 V 1.2000 V VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output 1.2125 V 1.2250 V 1.2375 V 1.2500 V 1.2625 V 1.2750 V 1.2875 V 1.3000 V 1.3125 V 1.3250 V 1.3375 V 1.3500 V 1.3625 V 1.3750 V 1.3875 V 1.4000 V 1.4125 V 1.4250 V 1.4375 V 1.4500 V 1.4625 V 1.4750 V 1.4875 V 1.5000 V 1.5125 V 1.5250 V 1.5375 V 1.5500 V 1.5625 V 1.5750 V 1.5875 V 1.6000 V
Rev. 0 | Page 11 of 28
ADP3190
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in Table 4. These limits are based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if all of the VID DAC inputs are high, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 250 s to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time based on the DELAY ramp. The PWRGD pin is held low until the DELAY pin reaches 2.6 V. The time between when the PWRGD undervoltage threshold is reached and when the DELAY pin reaches 2.6 V provides the turn-on delay time. This time is incorporated into the soft start ramp. To ensure a 1 ms delay time on PWRGD, the soft start ramp must also be >1 ms. Refer to the Application Information section for detailed information on setting CDLY.
OUTPUT ENABLE AND UVLO
For the ADP3191/ADP3191A to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold, and the EN pin must be higher than its logic threshold. If UVLO is less than the threshold or the EN pin is a logic low, the ADP3191/ADP3191A are disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3110 drivers. The ILIMIT being grounded disables the drivers, so that both the DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated during output due to the high current discharge of the output capacitors through the inductors.
OUTPUT CROWBAR
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 550 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
Rev. 0 | Page 12 of 28
L1 370nH 18A 2700F/16V/3.3 A x 2 SANYO MV-WX SERIES
+ +
R3 2.2
C8 15nF
VIN 12V RAMPADJ
1 BST DRVH SW PGND DRVL 5 6 7 2 IN 3 OD 4 VCC 8
VIN RTN C1 Q2 NTD40N03 Q1 NTD40N03 R 10
+
C2 L2 320nH/1.4m
+
D2 1N4148
U2 C6 ADP3110A 10nF
560F/4V x 8 SANYO SEPC SERIES 5m EACH
C7 4.7F
VCC(CORE) 0.8375V - 1.6V 95A TDC, 119A PK VCC(CORE) RTN
C5 4.7F R4 2.2 C12 15nF Q4 Q3 NTD110N02 NTD110N02 C22
C31
10F
D3 1N4148 C10 U3 ADP3110A 10nF
1 BST DRVH SW PGND DRVL 5 6 7 2 IN 3 OD 4 VCC 8 C11 4.7F
Q6 NTD40N03 Q5 NTD40N03
x 18 MLCC IN SOCKET L3 320nH/1.4m R 10
D1 1N4148 240 C9 4.7F C3 100F (OPTIONAL) D4 1N4148
1 BST 2 IN 3 OD DRVH SW PGND 4 VCC DRVL +
1FOR A DESCRIPTION OF OPTIONAL R SW RESISTORS, SEE THE THEORY OF OPERATION SECTION.
U1 ADP3191
1 2 3 4 5
C4 1F
R5 2.2
C16 15nF
Q7 Q8 NTD110N02 NTD110N02
VID4 VID3 VID2 VID1 VID0 RSW11 RSW21 RSW31 RSW41 RPH4 158k 1% RPH3 158k 1% 84.5k RCS2 RPH1 158k 1% RPH2 158k 1% C13 4.7F R6 2.2 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ ILIMIT 15 CSREF 16 CCS1 560pF
C23 10nF
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 RCS1 CCS2 1.5nF 35.7k
C14 U4 ADP3110A 10nF
8 7 6 5
C15 4.7F Q10 NTD40N03 Q9 NTD40N03
FROM CPU
Figure 9. Typical VR101 Applications Schematic (ADP3191 Only; See Figure 18 for ADP3191A Connections)
L4 320nH/1.4m R 10 Q12 Q11 NTD110N02 NTD110N02 C20 15nF
6 7 8 9 10 11 12 13 14
Rev. 0 | Page 13 of 28
D5 1N4148 C18 U5 ADP3110A 10nF
1 BST 2 IN DRVH SW 8 7
C22 1nF
CB 470pF
CFB 22pF
POWER GOOD
RB 1.21k
CA RA 470pF 12.1k
ENABLE
C19 4.7F Q14 NTD40N03 Q13 NTD40N03 R7 10 C17 4.7F
3 OD 4 VCC PGND DRVL 6 5
CDLY 39nF
RDLY 470k
RT 130k 1%
L5 320nH/1.4m R 10 RTH1 100k, 5% NTC
C21 100pF
R2 357k 1% RLIM 150k 1% R 1k
Q15 NTD110N02
Q16 NTD110N02
C 0.1F
RAMPADJ
ADP3191
05648-024
ADP3191 APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10.1-compliant CPU application are as follows: * * * * * * Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.300 V Duty cycle (D) = 0.108 Nominal output voltage at no load (VONL) = 1.281 V Nominal output voltage at 101 A load (VOFL) = 1.180 V Static output voltage drop based on a 1.0 m load line (RO) from no load to full load (VD) = VONL - VOFL = 1.281 V - 1.180 V = 101 mV Maximum output current (IO) = 119 A Maximum output current step (IO) = 95 A Number of phases (n) = 4 Switching frequency per phase (fSW) = 330 kHz However, as long as RDLY is kept greater than 200 k, this effect is minor. The value for CDLY can be approximated using
VVID C DLY = 20 A - 2 x R DLY t SS x V VID
(2)
where tSS is the desired soft start time. Assuming an RDLY of 390 k and a desired soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CDLY is 39 nF. Once CDLY is chosen, RDLY can be calculated for the current-limit latch-off time using
RDLY = 1.96 x t DELAY C DLY
(3)
* * * *
If the result for RDLY is less than 200 k, a smaller soft start time should be considered by recalculating the equation for CDLY, or a longer latch-off time should be used. RDLY should never be less than 200 k. In this example, a delay time of 9 ms results in RDLY = 452 k. The closest standard 5% value is 470 k.
SETTING THE CLOCK FREQUENCY
The ADP3191/ADP3191A use a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and/or the input and output capacitors. With n = 4 for four phases, a clock frequency of 1.32 MHz sets the switching frequency (fSW) of each phase to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 3 shows that to achieve 1.32 MHz oscillator frequency, the correct value for RT is 130 k. Alternatively, the value for RT can be calculated using
RT = 1 - 31 k n x f SW x 4.7 pF
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. But it also allows using smaller inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses but requires larger inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor.
IR = VVID x (1 - D ) f SW x L
(1)
where 4.7 pF and 31 k are internal IC component values. For good initial accuracy and frequency stability, a 1% resistor is recommended.
(4)
SOFT START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES
Because the soft start and current-limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 A internal current source. The value of RDLY has a second-order impact on the soft start time because it sinks part of the current source to ground.
Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage.
L VVID x RO x (1 - (n x D )) f SW x VRIPPLE
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
L 1.3 V x 1.0 m x (1 - 0.432 ) = 224 nH 330 kHz x 10 mV
If the resulting ripple voltage is less than it was designed for, make the inductor smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling.
Rev. 0 | Page 14 of 28
ADP3191
The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 320 nH inductor is a good starting point and gives a calculated ripple current of 11 A. The inductor should not saturate at the peak current of 35.5 A and should be able to handle the sum of the power dissipation caused by the average current of 30 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR can cause excessive power losses, while too small a value can lead to increased measurement error. A good rule is to have the DCR be about 1 to 11/2 times the droop resistance (RO). For this design, an inductor with a DCR of 1.4 m is used.
Selecting a Standard Inductor
The following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request: * * * Coilcraft www.coilcraft.com Sumida Electric Company www.sumida.com Vishay Intertechnology www.vishay.com
OUTPUT DROOP RESISTANCE
The design requires the regulator output voltage measured at the CPU pins to drop when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). The output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. This summer filter is the CS amplifier configured with RPH(X) (summers), RCS, and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors:
RO = RCS x RL RPH ( x )
DESIGNING AN INDUCTOR
Once the inductance and DCR are known, the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to control the accuracy of the system. 15% inductance and 8% DCR (at room temperature) are reasonable tolerances most manufacturers can meet. The first decision in designing the inductor is to choose the core material. Several possibilities for providing low core loss at high frequencies include the powder cores (for example, KoolM from Magnetics, Inc. or from Micrometals) and the gapped soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choice for a core geometry is a closed-loop type such as a potentiometer core, PQ, U, or E core or toroid. A good compromise between price and performance is a core with a toroidal shape. Many useful magnetics design references are available for quickly designing a power inductor, such as * * Magnetic Designer Software Intusoft (www.intusoft.com) Designing Magnetic Components for High-Frequency DCDC Converters, by William T. McLyman, KG Magnetics, Inc., ISBN 1883107008
(6) (7)
CCS =
L RL x RCS
The user has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 k and then solve for RPH(X) by rearranging Equation 6.
RPH ( x ) = RL x RCS RO 1.4 m x 100 k = 140 k 1.0 m
RPH ( x ) =
Next, use Equation 6 to solve for CCS.
CCS = 320 nH = 2.28 nF 1.4 m x 100 k
It is best to have a dual location for CCS in the layout, so that standard values can be used in parallel to get as close as possible to the value desired. For accuracy, CCS should be a 5% or 10% NPO capacitor. This example uses a 5% combination for CCS of 1.5 nF and 560 pF in parallel. Recalculating RCS and RPH(X) using this capacitor combination yields 110 k and 154 k. The closest standard 1% value for RPH(X) is 158 k.
Rev. 0 | Page 15 of 28
ADP3191
INDUCTOR DCR TEMPERATURE CORRECTION
With the inductor's DCR being used as the sense element and copper wire being the source of the DCR, compensation is needed for temperature changes of the inductor's winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, Resistor RCS1 and Resistor RCS2 are needed. See Figure 10 to linearize the NTC and produce the desired temperature tracking.
PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW-SIDE MOSFET TO SWITCH NODES TO VOUT SENSE
4.
Compute the relative values for RCS1, RCS2, and RTH using
RCS2 =
( A - B ) x r1 x r2 - A x (1 - B ) x r2 + B x (1 - A) x r1 A x (1 - B ) x r1 - B x (1 - A ) x r2 - ( A - B )
(1 - A ) 1 A - 1 - RCS2 r1 - RCS2
1 1 1 - 1 - RCS2 RCS1 (8)
RCS1 =
RTH =
5.
ADP3191/ ADP3191A
RTH
Calculate RTH = rTH x RCS, then select the closest value of thermistor available. Also, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one:
k= RTH ( ACTUAL ) RTH (CALCULATED )
(9)
RPH1
RPH2
RPH3
CSCOMP
18
RCS1 CCS1 CCS2
RCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES
6.
Calculate values for RCS1 and RCS2 using Equation 10: RCS1 = RCS x k x RCS1 RCS2 = RCS x ((1 - k ) + (k x RCS2 )) (10)
CSSUM
17
CSREF
05648-011
16
Figure 10. Temperature Compensation Circuit Values
The following procedure and expressions yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value. 1. Select an NTC based on type and value. Because there isn't a value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures that work well are 50C and 90C. These resistance values are called A (RTH(50C)/RTH(25C)) and B (RTH(90C)/RTH(25C)). The NTC's relative value is always 1 at 25C. Find the relative values of RCS required for each of these temperatures. This is based on the percentage change needed, which in this example is initially 0.39%/C. These are called r1 (1/(1 + TC x (T1 - 25))) and r2 (1/(1 + TC x (T2 - 25))), where TC = 0.0039 for copper. T1 = 50C and T2 = 90C are chosen. From this, calculate that r1 = 0.9112 and r2 = 0.7978.
For this example, RCS has been calculated to be 110 k. Start with a thermistor value of 100 k. Next, look through the available 0603-size thermistors, and find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these, compute RCS1 = 0.3795, RCS2 = 0.7195, and RTH = 1.075. Solve for RTH, which yields 118.28 k. Then, choose 100 k, which makes k = 0.8455. Finally, RCS1 and RCS2 are 35.3 k and 83.9 k. Choose the closest 1% resistor values, which yields a choice of 35.7 k or 84.5 k.
OUTPUT OFFSET
The Intel specification requires that at no load should the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11:
B
2.
3.
RB =
VVID - VONL I FB
RB =
1.3 V - 1.281 V = 1.22 k 15.5 A
(11)
The closest standard 1% resistor value is 1.21 k.
Rev. 0 | Page 16 of 28
ADP3191
COUT SELECTION
The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Also, to determine what is required, use some simple design guidelines that are based on having both bulk and ceramic capacitors in the system. The first step is to select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18 of Size 1206 being the physical limit. Additional ceramic capacitors can be placed along the outer edge of the socket as well. Combined ceramic values of 200 F to 300 F are recommended, usually made up of multiple 10 F or 22 F capacitors. Select the number of ceramic capacitors, and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID on-the-fly voltage stepping of the output (Voltage Step VV in Time tV with error of VERR). A lower limit is based on meeting the capacitance for load release for a given maximum load step, IO, and a maximum allowable overshoot. The total amount of load release voltage is given as VO = IO x RO + Vrl, where Vrl is the maximum allowable overshoot voltage.
L x IO - Cz C x (MIN ) n x R + Vrl x V O VID I O
Cx ( MAX )
This example uses 18, 10 F 1206 MLC capacitors (CZ = 180 F). The VID on-the-fly step change is 450 mV in 230 s with a settling error of 2.5 mV. The maximum allowable load release overshoot for this example is 50 mV, so solving for the bulk capacitance yields
320 nH x 95 A C x (MIN ) - 180 F = 3.65 mF 4 x 1.0 m + 50 mV x 1.3 V 95 A
C x (MAX )
4 x 4.6 2 x (1.0 m )2 x 1.3 V
320 nH x 450 mV
x
2 230 s x 1.3 V x 4 x 4.6 x 1.0 m - 1 - 180 F = 1+ 450 mV x 320 nH
48.5 mF where K = 4.6. Using eight 560 F Al-Poly capacitors with a typical ESR of 5 m each yields CX = 4.48 mF with an RX = 0.63 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using Lx C z x RO 2 x Q 2 L x 180 F x (1 m )2 x 2 = 360 pH (14)
(12)
L
2 nK 2 RO
x
2 V VV nKRO - 1 - C z x 1 + t v VID x V VVID L V
(13)
where Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is approximately 350 pH for the eight A1-Polys capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. For this multimode control technique, all ceramic designs can be used as long as the conditions of Equation 11, Equation 12, and Equation 13 are satisfied.
V where K = 1n ERR V V
.
To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may need the switching frequency to increase to keep the output ripple the same).
Rev. 0 | Page 17 of 28
ADP3191
POWER MOSFETS
For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3110A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3191/ADP3191A, currents are balanced between phases; thus, the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO):
I PSF = (1 - D ) x O nSF 1 nI + x R 12 n SF
2
Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs:
PS ( MF ) = 2 x f SW x VCC x I O nMF
x RG x
nMF x C ISS n
(16)
where RG is the total gate resistance (2 for the ADP3110A and about 1 for typical high speed switching MOSFETs, making RG = 3 ), and CISS is the input capacitance of the main MOSFET. Adding more main MOSFETs (nMF) does not really help the switching loss per MOSFET because the additional gate capacitance slows switching. The best way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET:
I PC ( MF ) = D x O n MF 1 n x IR + x 12 n MF
2

2
x RDS (SF )
(15)

2
x R DS ( MF )
(17)
Knowing the maximum output current being designed for and the maximum allowed power dissipation, it is possible to find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50C, a safe limit for PSF is 1 W to 1.5 W at 120C junction temperature. Thus, for this example (119 A maximum), RDS(SF) (per MOSFET) < 7.5 m. This RDS(SF) is also at a junction temperature of about 120C, so be certain to account for this temperature when making this selection. This example uses two lower-side MOSFETs at 4.8 m each at 120C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3110A). The output impedance of the driver is approximately 2 , and the typical MOSFET input gate resistances are about 1 to 2 , so a total gate capacitance of less than 6000 pF should be adhered to. Because there are two MOSFETs in parallel, the input capacitance for each synchronous MOSFET should be limited to 3000 pF. The high-side (main) MOSFET has to be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off and to the current and voltage that are being switched.
Typically, for main MOSFETs, the highest speed (low CISS) device is preferred, but these usually have higher on resistance. Select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For this example, an NTD40N03L was selected as the main MOSFET (eight total; nMF = 8), with a CISS = 584 pF (maximum) and RDS(MF) = 19 m (maximum at TJ = 120C). An NTD110N02L was selected as the synchronous MOSFET (eight total; nSF = 8), with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 m (maximum at TJ = 120C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 119 A and IR = 11 A yields 958 mW for each synchronous MOSFET and 872 mW for each main MOSFET. These numbers comply with the guideline to limit the power dissipation to 1 W per MOSFET. One last thing to consider is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation, where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET:
f PDRV = SW x (nMF x QGMF + nSF x QGSF ) + I CC x VCC 2xn
(18)
Also shown is the standby dissipation factor (ICC x VCC) for the driver. For the ADP3110A, the maximum dissipation should be less than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC, and QGSF = 48 nC, 297 mW is found in each driver, which is below the 400 mW dissipation limit. See the ADP3110A data sheet for more details.
Rev. 0 | Page 18 of 28
ADP3191
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value:
RR = AR x L 3 x AD x RDS x C R 0.2 x 320 nH = 356 k 3 x 5 x 2.4 m x 5 pF
For values of RLIM greater than 500 k, the current limit can be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, choosing a peak current limit of 200 A for ILIM results in RLIM = 156 k, for which 150 k is chosen as the nearest 1% value. The limit of the per-phase current limit described earlier is determined by
I PHLIM VCOMP (MAX ) - V R - V BIAS AD x R DS (MAX ) + IR 2
(19)
(23)
RR =
where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor value. The closest standard 1% resistor value is 357 k. The internal ramp voltage magnitude can be calculated by using
VR = AR x (1 - D ) x VVID R R x C R x f SW
For the ADP3191/ADP3191A, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current-balancing amplifier gain (AD) is 5. Using VR of 0.49 V and RDS(MAX) of 3 m (low-side on resistance at 150C), calculate a per-phase peak current limit of 100 A. Although this number may seem high, this current level can be reached only with an absolute short at the output, and the current-limit latchoff function shuts down the regulator before overheating can occur. This limit can be adjusted by changing the ramp voltage (VR), but make sure not to set the per-phase limit lower than the average per-phase current (ILIM/n). The per-phase initial duty cycle limit is determined by
D MAX = D x VCOMP ( MAX ) - VBIAS VRT
0.2 x (1 - 0.108 ) x 1.3 V VR = = 390 m V 357 k x 5 pF x 330 kHz
(20)
The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response improve, but thermal balance degrades. Likewise, if the ramp is made smaller, thermal balance improves at the sacrifice of transient response and stability. The factor of 3 in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
(24)
In this example, the maximum duty cycle is 0.46.
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3191/ADP3191A allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. This ensures optimal positioning and allows minimization of the output decoupling. With the multimode feedback structure of the ADP3191/ ADP3191A, the feedback compensation must be set to make the converter's output impedance, working in parallel with the output decoupling, meet this goal. Several poles and zeros created by the output inductor and decoupling capacitors (output filter) need to be compensated for.
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input:
VRT = VR 2 x (1 - n x D ) 1 - nx f xC x R X SW O
(21)
In this example, the overall ramp signal is 0.49 V.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor value for RLIM. The current-limit threshold for the ADP3191/ADP3191A is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/A (ALIM). RLIM can be found using
RLIM = ALIM x VLIM I LIM x RO
(22)
Rev. 0 | Page 19 of 28
ADP3191
A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 25 to Equation 29 yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Layout and Component Placement section). The first step is to compute the time constants for all of the poles and zeros in the system.
RL x VRT 2 x L x (1 - n x D ) x VRT + VVID n x C X x RO x VVID
RE = n x RO + AD x RDS +
RE = 4 x 1 m + 5 x 2.4 m +
1.4 m x 0.49 V 1.3 V
+
2 x 320 nH x (1 - 0.432 ) x 0.49 V 4 x 4.45 mF x 1 m x 1.3 V
= 24.2 m
(25)
TA = C X x (RO - R) +
TB = (RX + R - RO ) x CX = (0.63 m + 0.5 m - 1 m) x 4.45 mF = 580 ns
A x R DS V RT x L - D 2 x f SW TC = VVID x R E 5 x 2.4 m 0.49 V x 320 nH - 2 x 330 kHz = 4.7 s = 1.3 V x 24.2 m
350 pH 1 m - 0.65 m LX RO - R x = 4.45 mF x (1 m - 0.5 m ) + x = 2.50 s 1 m 10.63 m RO RX
(27)
(26)
(28) = 333 ns (29)
TD =
C X x (RO - R' ) + CZ x RO
2 C X x CZ x RO
=
4.45 mF x (1 m - 0.5 m ) + 180 F x 1 m
4.45 mF x 180 F x (1 m )2
where, for the ADP3191/ADP3191A, R' is the PCB resistance from the bulk capacitors to the ceramics and RDS is the total low-side MOSFET on resistance per phase. In this example, AD is 5, VRT equals 0.49 V, R' equals approximately 0.5 m (assuming a 4-layer, 1-ounce motherboard), and LX equals 350 pH for the eight Al-Poly capacitors. The compensation values can then be solved using the following:
CA = n x RO x TA RE x RB
(30)
CA =
RA =
4 x 1 m x 2.50 s 24.2 m x 1.21 k
= 342 pF
TC 4.7 s = = 13.7 k C A 342 pF
(31) (32) (33)
CB = CFB =
580 ns TB = = 479 nF RB 1.21 k 333 ns TD = = 24.3 pF RA 13.7 k
These are the starting values, prior to tuning the design, to account for layout and other parasitic effects (see the Layout and Component Placement section). The final values selected after tuning are CA = 470 pF RA = 12.1 k CB = 470 pF CFB = 22 pF
B
Rev. 0 | Page 20 of 28
ADP3191
Figure 11 and Figure 12 show the typical transient response using these compensation values.
CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION
In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of one-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor, sized for the maximum rms current, must be used. The maximum rms capacitor current is given by
I CRMS = D x I O x 1 -1 NxD
(34)
05648-012
I CRMS = 0.108 x 119 A x
1 - 1 = 14.7 A 4 x 0.108
Figure 11. Typical Transient Response for Design Example Load Step
The capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors can be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by two 2700 F, 16 V aluminum electrolytic capacitors and eight 4.7 F ceramic capacitors. To reduce the input current di/dt to a level below the recommended maximum of 0.1 A/s, an additional small inductor (L > 370 nH at 18 A) should be inserted between the converter and the supply bus. This inductor also acts as a filter between the converter and the primary power source.
05648-013
100
Figure 12. Typical Transient Response for Design Example Load Release
EFFICIENCY (%)
80
60
40
20
05648-014
VOUT = 1.3V TA = 25C 0 0 20 40 60 80 100 120
OUTPUT CURRENT (A)
Figure 13. Efficiency of the Circuit of Figure 10 vs. Output Current
Rev. 0 | Page 21 of 28
ADP3191
TUNING THE ADP3191/ADP3191A
1. 2. Build a circuit based on the compensation values computed from the design spreadsheet. Hook up the dc load to circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. 6. Measure the output voltage from no load to full load, using 5 A steps. Compute the load line slope for each change, and then average to get the overall load line slope (ROMEAS). If ROMEAS is off from RO by more than 0.05 m, use the following to adjust the RPH values:
RPH ( NEW ) = RPH (OLD ) x ROMEAS RO
7.
DC Load Line Setting
3. 4. Measure the output voltage at no load (VNL). Verify it is within tolerance. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2, using Equation 35 and Equation 36.
RCS2 ( NEW ) = RCS2 (OLD ) x V NL - VFLCOLD V NL - VFLHOT
(36)
8. 9.
Repeat Step 6 and Step 7 to check the load line, and repeat adjustments if necessary. Once dc load line adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure.
10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications.
(35)
5.
Repeat Step 4 until the cold and hot voltage measurements remain the same.
RCS1( NEW ) =
1 RCS1(OLD ) x RTH (25C ) + (RCS1(OLD ) - RCS2 ( NEW ) ) x (RCS1(OLD ) - RTH (25 C ) ) RCS1(OLD ) + RTH (25C ) - 1 RTH (25 C )
(37)
Rev. 0 | Page 22 of 28
ADP3191
AC Load Line Setting
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling, with the time scale at 100 s/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with a 50% duty cycle. 14. Measure the output waveform (if not visible, use dc offset on scope to view). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 14.
VDROOP
Initial Transient Setting
18. With the dynamic load still set at the maximum step size, expand the scope time scale to see 2 s/div to 5 s/div. The waveform may have two overshoots and one minor undershoot (see Figure 15). Here, VDROOP is the final desired value.
VTRAN1
VTRAN2
05648-016
VACDRP VDCDRP
Figure 15. Transient Setting Waveform
19. If both overshoots are larger than desired, try making the following adjustments:
05648-015
* * *
Make the ramp resistor larger by 25% (RRAMP). For VTRAN1, increase CB, or increase the switching frequency.
B
Figure 14. AC Load Line Waveform
15. Use the horizontal cursors to measure VACDRP and VDCDRP, as shown. Do not measure the undershoot or overshoot that happens immediately after this step. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 38 to adjust CCS. It may be necessary to parallel different values to get the correct one, because there are limited standard capacitor values available. It is a good idea to have locations for two capacitors in the layout for this.
C CS ( NEW ) = C CS (OLD ) x V ACDRP V DCDRP
For VTRAN2, increase RA, and decrease CA by 25%.
If these adjustments do not change the response, the output decoupling is the limiting factor. Check the output response every time a change is made, or nodes are switched, to make sure the response remains stable. 20. For load release (see Figure 16), if VTRANREL is larger than VTRAN1 (see Figure 15), there is not enough output capacitance. Either more capacitance is needed or the inductor values need to be smaller. If inductors are changed, start the design again using the spreadsheet and this tuning procedure.
(38)
16. Repeat Step 11 to Step 13, and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. 17. Set the dynamic load step to maximum step size. Do not use a step size larger than needed, and verify that the output waveform is square, which means that VACDRP and VDCDRP are equal.
VTRANREL
VDROOP
Figure 16. Transient Setting Waveform
Rev. 0 | Page 23 of 28
05648-017
ADP3191
Because the ADP3191/ADP3191A turn off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. Thus, headroom does not need to be added for ripple, allowing the load release, VTRANREL, to be larger than VTRAN1 by the amount of ripple and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, this implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications.
CHOOSING BETWEEN THE ADP3191 AND THE ADP3191A
For existing designs using the ADP3181, the ADP3191 is the recommended replacement. For new designs, where 5 V system voltage is available, it is recommended to use the ADP3191A, as configured in Figure 18. For correct power sequencing, ensure that the 12 V rail is present before the 5 V VIN is applied to the ADP3191A.
VIN 12V 370nH 18A 2700F/16V/3.3 A x 2 SANYO MV-WX SERIES
+ +
VIN 5V
REPLACING THE ADP3181 WITH THE ADP3191
Figure 17 shows the changes needed when replacing an existing ADP3181 design with the ADP3191.
VIN 12V 370nH 18A 2700F/16V/3.3 A x 2 SANYO MV-WX SERIES
+ +
VIN RTN
U1 ADP3191A
1 2 3
10 0603 1/8W
+
VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 ILIMIT 15
05648-026
1F
100F
1N4148 VIN RTN
4 5
ADP3191 240 1206 1/4W
+
6 7 8
U1 ADP3191
1 2 3 4 5 6 7 8 9
100F
1F
R 1k C 0.1F 357k 1%
9 10 11 12 13 14
VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 ILIMIT 15
05648-025
Figure 18. Replacing the ADP3181 with the ADP3191A
RAMPADJ FILTER
It is recommended that a filter be placed on the RAMPADJ line. In designs using the ADP3181, the RAMPADJ and the VCC were typically both connected to the 12 V input supply. Therefore, the RAMPADJ could use the decoupled VCC line as its input. On the ADP3191, the VCC is 5 V, but the RAMPADJ still needs to be connected to the 12 V input supply. Therefore, the filter is needed to remove noise from the 12 V input supply. A 1 k resistor and 0.1 F cap are recommended for this filter.
R 1k C 0.1F 357k 1%
10 11 12 13 14
Figure 17. Replacing the ADP3181 with the ADP3191
Rev. 0 | Page 24 of 28
ADP3191
SHUNT RESISTOR DESIGN
When replacing an existing ADP3181 design with the ADP3191, the shunt resistor value needs to be determined. A trade-off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 19 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages. The maximum power dissipated is calculated using Equation 39.
Example: UVLO voltage specification = 8 V.
From Figure 19, a shunt resistor value of 420 is recommended. From Figure 19, the power dissipation will be 140 mW. The user can choose any of the following: * * * Two 840 , 0603 resistors in parallel Two 840 , 0805 resistors in parallel One 420 , 1206 resistor
9.5 0.40 RSHUNT 9.0 0.35
PMAX =
where:
(V
IN ( MAX )
- VCC ( MIN ) )
2
RSHUNT
(39)
8.5
0.30
VIN(MAX) is the maximum voltage from the 12 V input supply. (If the 12 V input supply is 12 V 5%, then VIN(MAX) = 12.6 V. If the 12 V input supply is 12 V 10%, then VIN(MAX) = 13.2 V.) The graph shows the power when VIN(MAX) = 12.6 V. VCC(MIN) is the minimum VCC voltage of the ADP3191. It is specified as 4.75 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface mount resistors is 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W.
8.0
0.25
7.5
0.20
7.0 PSHUNT 6.5 100 200 300 400 RSHUNT () 500 600
0.15
05648-028
0.10 700
Figure 19. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltages
Rev. 0 | Page 25 of 28
POWER (mW)
UVLO (V)
ADP3191 LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
POWER CIRCUITRY RECOMMENDATIONS
* The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. Whenever a power dissipating component, (for example, a power MOSFET), is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. This improves current rating through the vias and also improves thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components.
GENERAL RECOMMENDATIONS
* For good results, a PCB with at least four layers is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output power; and wide interconnection traces in the remainder of the power delivery current paths. Note: Each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. * Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths. Then, the resistance and inductance introduced by these current paths is minimized, and the via current rating is not exceeded. If critical signal lines, including the output voltage sense lines of the ADP3191/ADP3191A, must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground noisier. Use an analog ground plane around and under the ADP3191/ADP3191A as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and not tied to any other power circuitry. This prevents power currents from flowing in the ground plane. Locate the components around the ADP3191/ADP3191A close to the controller with short traces. The most important traces to keep short, and away from other traces, are the FB pin and the CSSUM pin. Connect the output capacitors as close as possible to the load (or connector), for example, a microprocessor core that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, as described in the Power Circuitry Recommendations section.
*
*
*
*
*
*
SIGNAL CIRCUITRY RECOMMENDATIONS
* The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential-mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.
*
*
Rev. 0 | Page 26 of 28
ADP3191 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 20. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
0.394 0.390 0.386
28
15
0.158 0.154 0.150
1 14
0.244 0.236 0.228
PIN 1 0.065 0.049 0.069 0.053 8 0
0.010 0.004 COPLANARITY 0.004
0.025 BSC
0.012 0.008
SEATING PLANE
0.010 0.006
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AF
Figure 21. 28-Lead Shrink Small Outline Package [QSOP] (RQ-28) Dimensions shown in inches
ORDERING GUIDE
Model ADP3191JRUZ-RL 1 ADP3191JRQZ-RL1 ADP3191AJRUZ-RL1 ADP3191AJRQZ-RL1
1
Temperature Range 0C to 85C 0C to 85C 0C to 85C 0C to 85C
Package Description 28-Lead TSSOP 13" Reel 28-Lead QSOP 13" Reel 28-Lead TSSOP 13" Reel 28-Lead QSOP 13" Reel
Package Option RU-28 RQ-28 RU-28 RQ-28
Ordering Quantity 2500 2500 2500 2500
Z = Pb-free part.
Rev. 0 | Page 27 of 28
ADP3191 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05648-0-3/06(0)
T T
Rev. 0 | Page 28 of 28

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